1. Field Of The Invention
The present invention relates to interconnect technology such as is used in integrated circuit technology and general interconnect substrate technology. More particularly, the present invention relates to user-configurable interconnections in integrated circuits and interconnection substrates and to a network of user-configurable interconnections for integrated circuits and interconnection substrates.
2. The Prior Art
Numerous schemes for providing integrated circuit interconnections are known in the prior art. Various ones of these schemes relate to user-configurable interconnections for use in integrated circuits, wherein a plurality of potential interconnection points are fabricated into an integrated circuit during the manufacturing process, but the particular interconnections between circuit nodes in the integrated circuit are made by the user by programming selected ones of the interconnections such that desired connections between circuit nodes are made while other potential interconnections are deliberately unrealized.
More recently, general interconnect schemes, which may be realized on non-integrated circuit substrates, such as thick-film and thin-film hybrids and printed circuit boards, have begun to be investigated. Interconnect matrix applications and other non-integrated circuit applications employing user-configurable interconnections between conductors are possible.
There are several types of user-configurable interconnect schemes which are currently available to the designer. One type of user-configurable interconnect is reprogrammable, and can be altered by a user after initial circuit configuration has been accomplished. In integrated circuits, this type of interconnect may be implemented by simple transistors whose gate voltages are controlled to determine the interconnections to be made, or by one form or another of non-volatile memory devices, such as EPROMS, EEPROMS, NOVRAMS, or combinations of both simple transistors and non-volatile memory elements. An example of a technology for implementing this type of interconnect is found in U.S. Pat. No. 4,870,302 to Freeman.
Another type of user-configurable interconnect element is one-time programmable, and once initially configured, may not be reconfigured. This type of user-configurable interconnect may take one of two forms, a first form, normally short circuited until rendered an open circuit as a result of a programming procedure, and a second form normally open circuited until rendered a short circuit as a result of a programming procedure.
The first form of one-time user-programmable interconnect is usually referred to as fuse technology, and is exemplified by the disclosure found in U.S. Pat. No. 4,796,075 to Whitten. The second form of one-time user-programmable interconnect is usually referred to as antifuse technology, and is exemplified by the disclosure found in U.S. Pat. No. 4,823,181 to Mohsen et al. and U.S. Pat. No. 4,899,205 to Hamdy et al.
While each form of one-time user-programmable interconnect technology has been and continues to be useful in numerous integrated circuit and general conductor interconnect applications, there remains room for improvement of this technology. For example, interconnect networks comprising fuse technology initially present a network of connected nodes. Fuses connecting unwanted circuit paths are then programmed by applying a voltage or current source across them. One disadvantage of this method is that other fuses in the interconnection network which are not to be programmed are in the current path of the fuse to be programmed. Depending on the configuration of the particular network, these "sneak" paths for current can be significant enough to require a large amount of current to be supplied to program the desired fuses.
When antifuse technology is used, care must be taken to avoid the inadvertent programming of antifuses which are intended to remain unprogrammed. In some cases, the existence of parallel current and voltage paths through the potential interconnection networks raises the possibility of stressing antifuses which are to remain unprogrammed. Overly stressed antifuses may inadvertently become programmed, or may become so weakened that they will present a reliability problem and shorten the operating lifetime of the circuit in which they are used. This consideration necessitates careful design of the programming process and may also affect circuit design considerations.
It is an object of the present invention to provide an interconnection network for use in integrated circuits and general electronic/conductor interconnection networks which minimizes or eliminates the disadvantages of fuse and antifuse based interconnection networks.